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Multi Voltage SoC Power Design Technique

VLSI Design & Verification / 22/09/2022

Minimizing power consumption is a major factor that contributes to the modern-day development of IC designs, especially in the consumer electronics segment. The heating of the devices, the time it takes to turn on/off the features of handheld devices, battery life, etc are still under reforms. Hence it becomes important that best practices of chip design are adopted to aid the power consumption in SoCs (System on Chip) and other ICs (Integrated Circuit). According to market Research Future, the global System-on-Chip market was valued at USD 131.83 billion in 2021, and it is predicted to reach USD 214.8 Billion by the end of 2030, with a CAGR of 8.30 % from 2021 to 2030. The performance of the Silicon is greatly influenced by power management for SoCs and RTL designs. To attain power statistics, industries utilize power-aware designs. This blog’s focus is on multi-Voltage design terminology that can be used in HDL coding to determine silicon’s power performance. These aid in comprehending the design parameters when putting into practice power-conscious designs.

Multiple Voltage Design (Multi Voltage Power Domain) Method

Power supply has a direct relationship with dynamic power which consists of switching & short-circuit power. Therefore, reducing power naturally enhances power performance. The decreased threshold voltage causes an increase in gate delay. Lowering the voltage of SoC blocks is perhaps, the first design implementation that is used to meet power performance goals. In Figure 1 the system shows different voltage levels.

Figure 1

Lowering the voltage, lowers the current flowing and increases the delay in the gates, and by that means, the designs may not be able to run at desired clock frequencies. Lowering the voltage may cost the performance statistics but the performance can still be met as seen in Figure 1. Here the VLSI chip performance is achieved by lowering individual voltages of different modules.
Figure 1 can also be referred to as a multi-VDD design. The logic is partitioned into different domains called power domains. The structural model or a gate-level netlist derived from behavioural Verilog uses a different voltage line for each domain. The individual domains can be run as per performance objectives. Figure 2 shows an elaboration of the same.

Figure 2

The power intent derived using the IEEE standard 1801-2018 Unified Power Format UPF 3.1 is used by many companies to define the power parameters of a chip. The power architect makes use of this technology to create files that describe the power and power control intent of an electric design. Supply sets, power switches, level shifters, and memory retention techniques are all included in the annotation. Power states, transitions, a collection of sim states, the pg (power/ground pin) type and function properties of nets, and the -update parameter to assist the gradual refinement of the power intent are all definable descriptions of the potential power applied to the electronic system.

Requirements to create a multi-voltage design

Level shifters
As shown in figure 3. level shifters will shift the level of voltages to ensure different modules operating at different voltages will operate correctly when LS (Level shifter) circuits are attached. The circuits are implemented in HDL, and they can also be made to implement the drive strength. The figure shows a low to high voltage level shifter (A) and a high to low voltage level shifter (B). Vi and Vo are the sources and destinations of different voltage levels in different modules.

Figure 3

Power gating
The method in figure 4 is referred to as Disconnecting the power of the gates which are not in use. The figure shows an implementation of such a situation. Power gating is used to reduce leakage power. This step is performed at an architecture level while computing the performance factors of the low power module, or module at a sleep state while other priority modules are ON, or module where power is to be disconnected by software, or while shutting down the power.
Power gating is significantly used while modern-day traditional terms like SLEEP/WAKE events of the device. The wakeup and sleep sequence follow certain architectural decisions to enable or disable a sequence of operations that controls the power logic of the chip.

Figure 4

Special care must be taken while implementing power gating as output signals from a power gated block pose special challenges. This considers isolation and retention strategies at the micro-Architecture level while performing the wake-up or sleep sequence. The placement of circuits of retention and isolation strategy in the circuits should not affect the power performance factors. Retention cells are used to save the state of the chip to use during the wakeup sequence of a module. Figure 5 shows a state being saved upon the assertion of the saving sequence. Vdd_sw (Switched supply voltage) is controlled by switch and Vdd is always on voltages to power up the circuit. When save (saving sequence) is asserted, the output of the module is latched and is available as feedback.

Figure 5

Figure 6 illustrates where isolation cells are introduced when a shutdown or a sleep phase is isolated from the receiving end. Isolation cells keep them turned off and block output to a predefined value. In these ways isolation cells are attached to reduce crowbar currents, thereby reducing power leakage.

Figure 6

Clock Gating
This method is referred to as turning off the clock transitions when the circuit does not encounter switching of internal signals when there is no activity to be performed. This help controls the frequency of transitions from the power equation. Almost all EDA tools identify and support this.

The complexity of SoCs has expanded, introducing new demands for power management. The supply of the various SoC power domains must be flexible enough to be controlled by developers to control power dissipation and improve battery autonomy. Careful power analysis and knowledge of the capabilities of the tools at hand are prerequisites for selecting the best solutions. Power-related crises can be prevented by analysing power demand as early as possible in the design flow. Power goals are also made simpler to achieve by early analysis because higher-level techniques save the most power.

At Softnautics, we provide comprehensive semiconductor design and verification services including end-to-end ASIC/FPGA/SoC design from idea to realization to deployment. Our RTL design team can create power intent at module-system as well as chip level to meet power statistics of a predefined specification. We also have VLSI design & verification teams to validate the same power intent using static or dynamic verification.

Read our success stories related to VLSI Design Services to know more about our high-performance silicon services.

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Model Compression Techniques for Edge AI

AI Engineering / 07/09/2022

Deep learning is growing at a tremendous pace in terms of models and their datasets. In terms of applications, the deep learning market is dominated by image recognition followed by optical character recognition, and facial and object recognition. According to Allied market research, the global deep learning market was valued at$ 6.85 billion in 2020, and it is predicted to reach $ 179.96 billion by 2030, with a CAGR of 39.2% percent from 2021 to 2030. Well, at one point in time it was believed that large and complex models perform better, but now it’s almost a myth. With the evolution of Edge AI, more and more techniques came in to convert a large and complex model into a simple model that can be run on edge and all these techniques combine to perform model compression.

What is Model Compression?

Model Compression is a process of deploying SOTA (state of the art) deep learning models on edge devices that have low computing power and memory without compromising on models’ performance in terms of accuracy, precision, recall, etc. Model Compression broadly reduces two things in the model viz. size and latency. Size reduction focuses on making the model simpler by reducing model parameters, thereby reducing RAM requirements in execution and storage requirements in memory. Latency reduction refers to decreasing the time taken by a model to make a prediction or infer a result. Model size and latency often go together, and most techniques reduce both.

Popular Model Compression Techniques

Pruning
Pruning is the most popular technique for model compression which works by removing redundant and inconsequential parameters. These parameters in a neural network can be connectors, neurons, channels, or even layers. It is popular because it simultaneously decreases models’ size and improves latency.

Pruning

Pruning can be done while we train the model or even post-training. There are different types of pruning techniques which are weight/connection pruning, Neuron Pruning, Filter Pruning, and Layer pruning..

Quantization:
As we remove neurons, connections, filters, layers, etc. in pruning to lower the number of weighted parameters, the size of the weights is decreased during quantization. Values from a large set are mapped to values in a smaller set in this process. In comparison to the input network, the output network has a narrower range of values but retains most of the information. For further details on this method, you may read our in-depth article regarding model quantization here.

Knowledge Distillation
In the Knowledge distillation process, we train a complex and large model on a very large dataset. After fine-tuning the large model, it works well on unseen data. Once achieved, this knowledge is transferred to smaller Neural Networks or models. Both, the teacher network (a larger model) and the student network (a smaller model) are used. There exist two aspects here which is, knowledge distillation in which we don’t tweak the teacher model whereas in transfer learning we use the exact model and weight, alter the model to some extent, and adjust it for the related task.

knowledge distillation system

The knowledge, the distillation algorithm, and the teacher-student architecture models are the three main parts of a typical knowledge distillation system, as shown in the diagram above.

Low Matrix Factorization:
Matrices form the bulk of most deep neural architectures. This technique aims to identify redundant parameters by applying matrix or tensor decomposition and making them into smaller matrices. This technique when applied on dense DNN (Deep Neural Networks) decreases the storage requirements and factorization of CNN (Convolutional Neural Network) layers and improves inference time. A weight matrix A with two dimensions and having a rank r can be decomposed into smaller matrices as below.

Low Matrix Factorization

Model accuracy and performance highly depend on proper factorization and rank selection. The main challenge in the low-rank factorization process is harder implementation and it is computationally intensive. Overall, factorization of the dense layer matrices results in a smaller model and faster performance when compared to full-rank matrix representation.

Due to Edge AI, model compression strategies have become incredibly important. These methods are complementary to one another and can be used across stages of the entire AI pipeline. Popular frameworks like TensorFlow and Pytorch now include techniques like Pruning and Quantization. Eventually, there will be an increase in the number of techniques used in this area.

At Softnautics, we provide AI Engineering and Machine Learning services with expertise on cloud platforms accelerators like Azure, AMD, edge platforms (FPGA, TPU, Controllers), NN compiler for the edge, and tools like Docker, GIT, AWS DeepLens, Jetpack SDK, TensorFlow, TensorFlow Lite, and many more targeted for domains like Multimedia, Industrial IoT, Automotive, Healthcare, Consumer, and Security-Surveillance. We collaborate with organizations to develop high-performance cloud-to-edge machine learning solutions like face/gesture recognition, people counting, object/lane detection, weapon detection, food classification, and more across a variety of platforms.

Read our success stories related to Machine Learning expertise to know more about our services for accelerated AI solutions.

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An overview of Embedded Machine Learning techniques and their associated benefits

AI Engineering, Platform Engineering / 01/08/2022

Owing to revolutionary developments in computer architecture and ground-breaking advances in AI & machine learning applications, embedded systems technology is going through a transformational period. By design, machine learning models use a lot of resources and demand a powerful computer infrastructure. They are therefore typically run-on devices with more resources, like PCs or cloud servers, where data processing is efficient. Machine learning applications, ML frameworks, and processor computing capacity may now be deployed directly on embedded devices, thanks to recent developments in machine learning, and advanced algorithms. This is referred to as Embedded Machine Learning (E-ML).

The processing is moved closer to the edge, where the sensors collect data, using embedded machine learning techniques. This aids in removing obstacles like bandwidth and connection problems, security breaches by data transfer via the internet, and data transmission power usage. Additionally, it supports the use of neural networks and other machine learning frameworks, as well as signal processing services, model construction, gesture recognition, etc. Between 2021 to 2026, the global market for embedded AI is anticipated to expand at a 5.4 percent CAGR and reach about USD 38.87 billion, as per the maximize market research group reports.

The Underlying Concept of Embedded Machine Learning

Today, embedded computing systems are quickly spreading into every sphere of the human venture, finding practical use in things starting from wearable health monitoring systems, wireless surveillance systems, networked systems found on the internet of things (IoT), smart appliances for home automation to antilock braking systems in automobiles. The Common ML techniques used for embedded platforms include SVMs (Support Vector Machine), CNNs (convolutional neural network), DNNs (Deep Neural networks), k-NNs (K-Nearest Neighbour), and Naive Bayes. Large processing and memory resources are needed for efficient training and inference using these techniques. Even with deep cache memory structures, multicore improvements, etc., general-purpose CPUs are unable to handle the high computational demands of deep learning models. The constraints can be overcome by utilizing resources such as GPU and TPU processors. This is mainly because sophisticated linear algebraic computations, such as matrix and vector operations, are a component of non-trivial deep learning applications. Deep learning algorithms can be run very effectively and quickly on GPUs and TPUs, which makes them ideal computing platforms.

Running machine learning models on embedded hardware is referred to as embedded machine learning. The latter works according to the following fundamental precept: While model execution and inference processes take place on embedded devices, the training of ML models like neural networks takes place on computing clusters or in the cloud. Contrary to popular belief, it turns out that deep learning matrix operations can be effectively carried out on hardware with constrained CPU capabilities or even on tiny 16-bit/32-bit microcontrollers.

The type of embedded machine learning that uses extremely small pieces of hardware, such as ultra-low-power microcontrollers, to run ML models is called TinyML.Machine Learning approaches can be divided into three main categories: reinforcement learning, unsupervised learning, and supervised learning. In supervised learning, labelled data can be learned; in unsupervised learning, hidden patterns in unlabelled data can be found; and in reinforcement learning, a system can learn from its immediate environment by a trial-and-error approach. The learning process is known as the model’s “training phase,” and it is frequently carried out utilizing computer architectures with plenty of processing power, like several GPUs. The trained model is then applied to new data to make intelligent decisions after learning. The inference phase of the implementation is what is referred to as this procedure. IoT and mobile computing devices, as well as other user devices with limited processing resources, are frequently meant to do the inference.

Machine Learning Techniques

Application Areas of Embedded Machine Learning

Intelligent Sensor Systems
The effective application of machine learning techniques within embedded sensor network systems is generating considerable interest. Numerous machine learning algorithms, including GMMs (Gaussian mixture model), SVMs, and DNNs, are finding practical uses in important fields such as mobile ad hoc networks, intelligent wearable systems, and intelligent sensor networks.

Heterogeneous Computing Systems
Computer systems containing multiple types of processing cores are referred to as heterogeneous computing systems. Most heterogeneous computing systems are employed as acceleration units to shift computationally demanding tasks away from the CPU and speed up the system. Heterogeneous Multicore Architecture is an area of application where to speed up computationally expensive machine learning techniques, the middleware platform integrates a GPU accelerator into an already-existing CPU-based architecture thereby enhancing the processing efficiency of ML data model sets.

Embedded FPGAs
Due to their low cost, great performance, energy economy, and flexibility, FPGAs are becoming increasingly popular in the computing industry. They are frequently used to pre-implement ASIC architectures and design acceleration units. CNN Optimization using FPGAs and OpenCL-based FPGA Hardware Acceleration are the areas of application where FPGA architectures are used to speed up the execution of machine learning models.

Benefits

Efficient Network Bandwidth and Power Consumption
Machine learning models running on embedded hardware make it possible to extract features and insights directly from the data source. As a result, there is no longer any need to transport relevant data to edge or cloud servers, saving bandwidth and system resources. Microcontrollers are among the many power-efficient embedded systems that may function for long durations without being charged. In contrast to machine learning application that is carried out on mobile computing systems which consumes a substantial amount of power, TinyML can increase the power autonomy of machine learning applications to a greater extent for embedded platforms.

Comprehensive Privacy
Embedded machine learning eliminates the need for data transfer and storage of data on cloud servers. This lessens the likelihood of data breaches and privacy leaks, which is crucial for applications that handle sensitive data such as personal information about individuals, medical data, information about intellectual property (IP), and classified information.

Low Latency
Embedded ML supports low-latency operations as it eliminates the requirement of extensive data transfers to the cloud. As a result, when it comes to enabling real-time use cases like field actuating and controlling in various industrial scenarios, embedded machine learning is a great option.

Embedded machine learning applications are built using methods and tools that make it possible to create and deploy machine learning models on nodes with limited resources. They offer a plethora of innovative opportunities for businesses looking to maximize the value of their data. It also aids in the optimization of the bandwidth, space, and latencies of their machine learning applications.

Softnautics AI/ML experts have extensive expertise in creating efficient ML solutions for a variety of edge platforms, including CPUs, GPUs, TPUs, and neural network compilers. We also offer secure embedded systems development and FPGA design services by combining the best design methodologies with the appropriate technology stacks. We help businesses in building high-performance cloud and edge-based ML solutions like object/lane detection, face/gesture recognition, human counting, key-phrase/voice command detection, and more across various platforms.

Read our success stories related to Machine Learning expertise to know more about our services for accelerated AI solutions.

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Regression Testing in CI/CD and its Challenges

Quality Engineering / 22/07/2022

The introduction of the (Continuous Integration/Continuous Deployment) CI/CD process has strengthened the release mechanism, helping products to market faster than ever before and allowing application development teams to deliver code changes more frequently and reliably. Regression testing is the process of ensuring that no new mistakes have been introduced in the software after the adjustments have been made by testing the modified sections of the code as well as the parts that may be affected by the modifications. The Software Testing Market size is projected to reach $40 billion in 2020 with a 7% growth rate by 2027. Regression testing accounted for more than 8.5 percent of market share and is expected to rise at an annual pace of over 8% through 2027 as per the reports stated by the Global Market Insights group.

The Importance of Regression Testing

Regression testing is a must for large-sized software development teams following an agile model. When many developers are making multiple commits frequently, regression testing is required to identify any unexpected outcome in overall functionality caused by each commit, CI/CD setup identifies that and notifies the developers as soon as the failure occurs and makes sure the faulty commit doesn’t get shipped into the deployment.

There are different CI/CD tools available, but Jenkins is widely accepted because of being open source, hosts multiple productivity improvement plugins, has active community support, and can set up and scale easily. Source Code Management (SCM) platforms like GitLab and GitHub are also providing a good list of CI/CD features and are highly preferred when the preference is to use a single platform to manage code collaboration along with CI/CD.

Different level of challenges needs to be overcome when CI/CD setup is handling multiple software products with different teams, is using multiple SCMs like GitLab, GitHub, and Perforce, is required to use a cluster of 30+ high configuration computing hosts consisting of various operating systems and handling regression job count as high as 1000+. With the increasing complexity, it becomes important to have an effective notification mechanism, robust monitoring, balanced load distribution of clusters, and scalability and maintenance support along with priory management. In such scenarios, the role of the QA team would be helpful which can focus on CI/CD optimization and plays a significant part in shortening the time to market and achieving the committed release timeline.

Let us see the challenges involved in regression testing and how to overcome them in the blog ahead.

Effective notification mechanism

CI/CD tool like Jenkins provides plugin support to notify a group of people or a specific set of team members who are responsible to cause unexpected failures in the regression testing. Email notifications generated out of plugins are very helpful to bring attention to the underlying situation which needs to be fixed ASAP. But when there are plenty of such email notifications flooding the mailbox, it becomes inefficient to investigate each of them and has a high chance of being missed out. To handle such scenarios, a Failure Summary Report (FSR) highlighting new failures becomes helpful. FSR can further have an executive summary section along with detailed summary sections. Based on the project requirement, one can integrate JIRA, Jenkins links, SCM commit links, and time stamps to make it more useful for developers as the report will have all required references in a single document. FSR can be generated once or multiple times a day based on project requirements.

Optimum use of computing resources

When CI/CD pipelines are set up to use a cluster of multiple hosts with high computing resources, it is expected to have a minimum turnaround time of a regression run cycle with maximum throughput. To achieve this, regression runs need to be distributed correctly across the cluster. Workload management and scheduler tools like IBM LSF, and PBS can be used to run the jobs concurrently based on available computing resources at a given point in time. In Jenkins, one can add multiple slave nodes to distribute jobs across the cluster to minimize the waiting time in the Jenkins queue, but this needs to be done carefully based on available computing power after understanding the resource configuration of slave hosting servers, if not done carefully can result into node crash and loss of data.

Resource monitoring

To support the growing requirement of CI/CD, while scaling one can easily be missed to consider the disk space limitations or cluster resource limitations. If not handled properly, it results in CI/CD node crashes, slow executions, and loss of data. If such an incident happens when a team is approaching an import deliverable, it becomes difficult to meet the committed release timeline. Robust monitoring and notification mechanism should be in place to avoid such scenarios. One can-built monitoring application which continuously monitors the resources of each computing host, network disk space, and local disk space and raises a red flag when the set thresholds are crossed.

Scalability and maintenance

When regression job count grows to many 1000+, it becomes challenging to maintain them. A single change if manually needs to be done in many jobs becomes time-consuming and error-prone. To overcome this challenge, one should opt for a modular and scalable approach while designing test procedure run scripts. Instead of writing steps in CI/CD, one can opt to use SCM to maintain test run scripts. One can also use Jenkins APIs to update the jobs from the backend to save manual efforts.

Priority management

When regression testing of multiple software products is being handled in a single CI/CD setup, priority management becomes important. Pre-merge jobs should get prioritized over post-merge jobs, this can be achieved by running pre-merge jobs on a dedicated host by providing separate Jenkins slave and LSF queue. Post-merge Jenkins jobs of different products should be configured to use easy-to-update placeholders for Jenkins slave tags and LSF queues such that priorities can be easily altered based on which product is approaching the release.

Integration with third-party tools

When multiple SCMs like GitLab/GitHub and issue tracking tools like JIRA are used, tacking commits, MRs, PRs, and issue updates help the team to be in sync. Jenkins integration with GitLab/GitHub helps in reflecting pre-merge run results into SCM. By integrating an issue tracker like JIRA with Jenkins, one can create, and update issues based on run results. With SCM tools and JIRA integration, issues can be auto-updated on a new commit and PR merges.

Not only must regression test plans be updated to reflect new changes in the application code, but they must also be iteratively improved to become more effective, thorough, and efficient. A test plan should be viewed as an ever-evolving document. Regression testing is critical for ensuring high quality, especially as the breadth of the regression develops later in the development process. That’s why prioritization and automation of test cases are critical in Agile initiatives.

At Softnautics, we offer Quality Engineering Services for both software and embedded devices to assist companies in developing high-quality products and solutions that will help them succeed in the marketplace. Embedded and product testing, DevOps and test automation, Machine Leaning Application/Platform testing and compliance testing are all part of our comprehensive QE services. STAF, our in-house test automation framework, helps businesses test end-to-end products with enhanced testing productivity and a faster time to market. We also make it possible for solutions to meet a variety of industry standards, like FuSa ISO 26262, MISRA C, AUTOSAR, and others.

Read our success stories related to Quality Engineering services to know more about our expertise in the domain.

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Developing TPU based AI solutions using TensorFlow Lite

AI Engineering / 13/07/2022

AI has become ubiquitous today from personal devices to enterprise applications, you see them everywhere. The advent of IoT clubbed with rising demand for data privacy, low power, low latency, and bandwidth constraints has increasingly pushed for AI models to be running at the edge instead of the cloud. According to Grand View Research, the global edge artificial intelligence chips market was valued at USD 1.8 billion in 2019 and is expected to grow at a CAGR of 21.3 percent from 2020 to 2027. On this onset, Google introduced Edge TPU, also known as Coral TPU, which is its purpose-built ASIC for running AI at edge. It’s designed to give an excellent performance while taking up minimal space and power. When we train an AI model, we end up with AI models that have high storage requirements and GPU processing power. We cannot execute them on devices that have low memory and processing footprints. TensorFlow Lite is useful in this situation. TensorFlow Lite is an open-source deep learning framework that runs on the Edge TPU and allows for on-device inference and AI model execution. Also note that TensorFlow Lite is only for executing inference on the edge, not for training a model. For training an AI model, we must use TensorFlow.

Combining Edge TPU and TensorFlow Lite

When we talk about deploying an AI model on Edge TPU, we just cannot deploy any AI model.
The Edge TPU supports NN (Neural Network) operations and designs to enable high-speed neural network performance with low power consumption. Apart from specific networks, it only supports 8-bit quantized and compiled TensorFlow Lite models for Edge TPU.

For a quick summary, TensorFlow Lite is a lightweight version of TensorFlow specially designed for mobile and embedded devices. It achieves low latency results with a small storage size. There is a TensorFlow Lite converter that allows converting a TensorFlow-based AI model file (. pb) to a TensorFlow Lite file (.tflite). Below is a standard workflow for deploying applications on Edge TPU

Let’s look at some interesting real-world applications that can be built using TensorFlow Lite on edge TPU.

Human Detection and Counting

This solution has so many practical applications, especially in malls, retail, government offices, banks, and enterprises. One may wonder what one can do with detecting and counting humans. Data now has the value of time and money. Let us see how the insights from human detection and counting can be used.

Estimating Footfalls

For the retail industry, this is important as it gives an idea if their stores are doing well. Whether their displays are attracting customers to enter the shops. It also helps them to know if they need to increase or decrease support staff. For other organizations, they help in taking adequate security measures for people.

Crowd Analytics and Queue Management

For govt offices and enterprises, queue management via human detection and counting helps them manage longer queues and save people’s time. Studying queues can attribute to individual and organizations’ performance. Crowd detection can help analyze crowd alerts for emergencies, security incidents, etc., and take appropriate actions. Such solutions give the best results when deployed on edge, as required actions can be taken close to real-time.

Age and Gender-based Targeted Advertisements

This solution mainly has practical applications in the retail and advertisement industry. Imagine you walking towards the advertisement display which was showing a women’s shoe ad and then suddenly the advertisement changes to a male’s shoe ad as it determined you being male. Targeted advertisements help retailers and manufacturers target their products better and create brand awareness that a normal person would never get to see in his busy life.

This cannot be restricted to only advertisements, age and gender detection can also help businesses in taking quick decisions by managing appropriate support staff in retail stores, what age and gender people prefer visiting your store, businesses, etc. All this is more powerful and effective if you are very quick to determine and act. So, even more, a reason to have this solution on Edge TPU.

Face Recognition

The very first face recognition system was built in 1970, and to date this is still being developed, being made more robust and effective. The main advantage of having face recognition on edge is real-time recognition. Another advantage is having face encryption and feature extraction on edge, and just sending encrypted and extracted data to the cloud for matching, thereby protecting PII level privacy of face images (as you don’t save face images on edge and cloud) and complying with stringent privacy laws.

Edge TPU combined with the TensorFlow Lite framework opens several edges AI applications opportunities. As the framework is open-source the Open-Source Software (OSS) community also supports it, making it even more popular for machine learning use cases. The overall platform of TensorFlow Lite enhances the environment for the growth of edge applications for embedded and IoT devices.

At Softnautics, we provide AI engineering and machine learning services and solutions with expertise on edge platforms (TPU, Rpi, FPGA), NN compiler for the edge, cloud platforms accelerators like AWS, Azure, AMD, and tools like TensorFlow, TensorFlow Lite, Docker, GIT, AWS DeepLens, Jetpack SDK, and many more targeted for domains like Automotive, Multimedia, Industrial IoT, Healthcare, Consumer, and Security-Surveillance. Softnautics helps businesses in building high-performance cloud and edge-based ML solutions like object/lane detection, face/gesture recognition, human counting, key-phrase/voice command detection, and more across various platforms.

Read our success stories related to Machine Learning expertise to know more about our services for accelerated AI solutions.

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FPGA Market Trends With Next-Gen Technology

Platform Engineering, VLSI Design & Verification / 16/05/2022

Due to their excellent performance and versatility, FPGAs (Field Programmable Gate Arrays) appeal to a wide spectrum of businesses. Also, it has the feature of adopting new standards and modifying hardware as per the specific application requirement even after it’s been deployed for usage. ‘Gate arrays,’ on the other hand, relate to the architecture’s two-dimensional array of logic gates. FPGAs are used in several applications where complicated logic circuitry is required and changes are expected. Medical Devices, ASIC Prototyping, Multimedia, Automotive, Consumer Electronics, and many other areas are covered by FPGA applications. In recent years, market share and technological innovation in the FPGA sector is growing at a rapid speed. FPGAs offer benefits for Deep Learning and Artificial Intelligence based solutions, including an improved performance with low latency and high throughput, and power efficiency. According to Mordor Intelligence, the global FPGA market was valued at USD 6958.1 million in 2021, and it is predicted to reach USD 11751.8 million by 2027, with a CAGR of 8.32 percent from 2022 to 2027.

FPGA Design Market Drivers

Global Market Drivers

Let’s look at some interesting real-world applications that can be built using TensorFlow Lite on edge TPU.

The FPGA market is highly contested due to economies of scale, the nature of product offerings, and the cost-volume metrics favouring firms with low fixed costs. According to the size, 28nm FPGA chips are expected to grow rapidly because they provide high-speed processing and enhanced efficiency. These features have aided its adoption in a variety of industries, including automobiles, high-performance computing, and communications. The consumer electronics sector appears to be promising for FPGA since rising spending power in developing countries contributes to increased market demand for new devices. FPGAs are being developed by market players for use in IoT devices, Natural Language Processing (NLP), based infotainment, multimedia systems, and various industrial smart solutions. Based on the application requirement, either low-end, mid-range or high-end FPGA configurations are selected.

FPGA Architecture Overview

The general FPGA architecture design consists of three types of modules. They are I/O blocks, Switch Matrix, and Configurable Logic Blocks (CLB). FPGA is a semiconductor device made up of logic blocks coupled via programmable connections.

FPGA Architecture

The logic blocks are made up of look-up tables (LUTs) with a set number of inputs and are built using basic memory such as SRAM or Flash to hold Boolean functions. To support sequential circuits, each LUT is connected to a multiplexer and a flip-flop register. Similarly, many LUTs can be used to build for handling complex functions. As per the configurations FPGAs are classified into three types low-end, Mid-end & High-end FPGAs. Artix-7/Kintex-7 series from Xilinx, ECP3, and ECP5 series from Lattice semiconductor are some of the popular FPGA designs for low power & low design density. Whereas Virtex family from Xilinx, ProASIC3 family from Microsemi, Stratix family from Intel are designed for high performance with high design density.

FPGA Firmware Development

Since the FPGA is a programmable logic array, the logic must be configured to match the system’s needs. Firmware, which is a collection of data, provides the configuration. Because of the intricacy of FPGAs, the application-specific purpose of an FPGA is designed using the software. The user initiates the FPGA design process by supplying a Hardware Description Language (HDL) definition or a schematic design. VHDL (VHSIC Hardware Description Language) and Verilog are two commonly used HDLs. After that, the next step in the FPGA design process is to develop a netlist for the FPGA family being used. This is developed using an electronic design automation program and outlines the connectivity necessary within the FPGA. Afterward, the design is committed to the FPGA, which allows it to be used in the (ECB) electronic circuit board for which it was created.

Applications of FPGA

Automobiles
FPGAs in automobiles are extensively used in LiDAR to construct images from the laser beam. They’re employed in self-driving cars to instantly evaluate footage for impediments or the road’s edge for obstacle detection. Also, FPGAs are widely used in car-infotainment systems for reliable high-speed communications within the car. They enhance efficiency and conserve energy.

Tele-Communication Systems
FPGAs are widely employed in communication systems to enhance connectivity and coverage and improve overall service quality while lowering delays and latency, particularly when data alteration is involved. Nowadays FPGA is widely used in server and cloud applications by businesses.

Computer Vision Systems
These systems are becoming increasingly common in today’s world. Surveillance cameras, AI-bots, screen/character readers, and other devices are examples of this. Many of these devices necessitate a system that can detect their location, recognize things in their environment, and people’s faces, and act and communicate with them appropriately. This functionality necessitates dealing with large volumes of visual data, constructing multiple datasets, and processing them in real-time, this is where FPGA accelerates and makes the process much faster.

The FPGA market will continue to evolve as the demand for real-time adaptable silicon grows with next-gen technologies Machine Learning, Artificial Intelligence, Computer Vision, etc. The importance of FPGA is expanding due to its adaptive/programming capabilities, which make it an ideal semiconductor for training massive amounts of data on the fly. It is promising for speeding up AI workloads and inferencing. The flexibility, bespoke parallelism, and ability to be reprogrammed for numerous applications are the key benefits of using an FPGA to accelerate machine learning and deep learning processes.

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Machine Learning Based Facial Recognition and Its Benefits

AI Engineering / 09/05/2022

Machine Learning based facial recognition is a method of utilizing the face to identify or confirm one’s identity. Persons can be identified in pictures, films, or real time using facial recognition technology. Facial recognition has traditionally functioned in the same way as other biometric methods including voice recognition, eye irises, and fingerprint identification.

The growing use of facial recognition technology in a variety of applications is propelling the industry forward. In case of security, authorities are employing this technology to verify a passenger’s identity, particularly at airports. Face recognition software is also being used by law enforcement agencies to scan faces taken on CCTV and locate the suspect. Smartphones are another area of application where the technology has seen widespread adoption where the software is used to unlock the phone and verify payment information. As in the case of automotives self-driving cars are the focus of using this technology to unlock the car and act as the key to start/ stop the car. According to a report published by markets & markets group, the global facial recognition market is expected to grow at a CAGR of 17.2 percent over the forecast period, from USD 3.8 billion in 2020 to USD 8.5 billion in 2025.

Facial Recognition Technology Working Mechanism

A computer examines visual data and searches for a specified set of indicators, such as a person’s head shape, depth of their eyelids, etc. A database of facial markers is built, and an image of a face that matches the database’s essential threshold of resemblance suggests a possible match. Face recognition technologies, such as machine vision, modelling and reconstruction, and analytics, require the utilization of advanced algorithms in the areas of Machine Learning – Deep Learning and CNN (Convolutional Neural Network), which is growing at an exponential rate.

As facial recognition technology has progressed, a variety of systems for mapping faces and storing facial data have evolved based on Computer Vision, Deep Learning each with various degrees of accuracy and efficiency. In general, there exist 3 methods, which are as follows.

Traditional facial recognition
Biometric facial recognition
3D facial recognition

Traditional Facial Recognition

There are two methods to it. One is holistic facial recognition, in which an identifier’s complete face is analysed for identifying traits that match the target. Feature-based facial recognition, on the other hand, separates the relevant recognition data from the face before applying it to a template that is compared against prospective matches.

Detection – Facial recognition software detects the identifier’s face in an image
Analysis – Algorithms determine the unique facial biometrics and features, such as the distance between nose and mouth, size of eyelids, forehead, and other characteristics
Identification – The software can now compare the target faceprint to other faceprints in the database to find a match

Overview of Facial Recognition System

Biometric Facial Recognition

Skin and face biometrics are a growing topic in the field of facial recognition that has the potential to improve the accuracy of facial recognition technologies dramatically. A skin texture analysis examines a specific area of a subjects’ skin, using an algorithm to take very precise measurements of wrinkles, textures, and pores.

3D Facial Recognition

It’s a technique that uses the three-dimensional geometry of the human face to create a three-dimensional model of the facial surface. It employs specific aspects of the face to identify the subject, such as the curvature of the eye socket, nose, and chin, where hard tissue and bone are most visible. These regions are all distinct from one another and do not change throughout time. 3D face recognition can achieve more accuracy than its 2D counterpart by analysing the geometry of hard properties on the face. In the 3D facial recognition technology, sensors are employed to capture the shape of the face with more precision. Unlike standard facial recognition systems, 3D facial recognition is unaffected by light, and scans can even be done in complete darkness. Another advantage of 3D facial recognition is that it can recognize a target from many angles rather than just a straight-on appearance.

Applications of Facial Recognition Technology Retail

Face recognition in retail opens an ample number of possibilities for elevating the customer experience. Store owners can collect data about their customers’ visits (such as their reactions to specific products and services) and then conclude how to personalize their offerings. They can offer unique product packages to the clients based on their previous purchasing history and insights. Vending machines in Japan, for example, proposes drinks to customers based on their gender and age using facial recognition technology.

Healthcare

It has enhanced patient experience and reduced efforts for healthcare professionals by improving security and patient identification, as well as better patient monitoring and diagnosis. When a patient walks into the clinic, the facial recognition system scans their face and compares it to a database held by the hospital. Without the need for paperwork or other identification documents, the patient’s identity and health history are verified in real-time.

Security Companies

Nowadays machines that can effectively recognize individuals open a host of options for the security industry, the most important of which is the potential to detect illicit access to areas where non-authorized people are prohibited. Artificial intelligence-powered face recognition software can help spot suspicious behaviour, track down known offenders, and keep people safe in crowded locations.

Fleet Management Services

Facial recognition could be used in fleet management to give alerts to unauthorized personnel attempting to obtain access to vehicles, preventing theft. The fact that distraction is the major cause of accidents, which is due to the usage of electronic gadgets. When a driver’s eyes aren’t on the road, facial recognition technology may be designed to detect it. It may also be trained to detect eyes that indicate an intoxicated or tired driver, improving the safety of driver & fleet vehicles.

Benefits of Facial Recognition Technology

With constantly evolving capabilities, it will be fascinating to see where Machine Learning based Facial Recognition technology will reach over next decade. The amount and quality of image data required to train any facial recognition program are critical to its performance. Many examples are required, and each one necessitates a significant number of pictures to develop a thorough comprehension of the face.

At Softnautics we offer Machine Learning services to assist organizations in the development of futuristic AI solutions like facial recognition systems, Machine Learning/Deep Learning algorithms that compare facial features to several data sets using random and view-based features, utilizing complex mathematical representations and matching methods. We develop powerful Machine Learning models for feature analysis, neural networks, eigenfaces, and automatic face recognition. We provide Machine Learning services and solutions with expertise on edge platforms (TPU, RPi), NN compiler for the edge, Computer Vision, Machine Vision, tools like TensorFlow, TensorFlow Lite, Docker, GIT, AWS deepLens, Jetpack SDK, and many more targeted for domains like Automotive, Multimedia, Industrial IoT, Healthcare, Consumer, and Security-Surveillance.

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Model Quantization for Edge AI

AI Engineering / 29/04/2022

Deep learning is witnessing a growing history of success, however, the large/heavy models that must be run on a high-performance computing system are far from optimal. Artificial intelligence is already widely used in business applications. The computational demands of AI inference and training are increasing. As a result, a relatively new class of deep learning approaches known as quantized neural network models has emerged to address this disparity. Memory has been one of the biggest challenges for deep learning architectures. It was an evolution of the gaming industry that led to the rapid development of hardware leading to GPUs that enables 50 layer networks of today. Still, the hunger for memory by newer and powerful networks is now pushing for evolutions of Deep Learning model compression techniques to put a leash on this requirement, as AI is quickly moving towards edge devices to give near to real-time results for captured data. Model quantization is one such rapidly growing technology that has allowed deep learning models to be deployed on edge devices with less power, memory, and computational capacity than a full-fledged computer.

How did AI Migrate from Cloud to Edge?

Edge AI mostly works in a decentralized fashion. Small clusters of computer devices now work together to drive decision-making rather than going to a large processing center. Edge computing boosts the device’s real-time response significantly. Another advantage of edge AI over cloud AI is the lower cost of operation, bandwidth, and connectivity. Now, this is not easy as it sounds. Running AI models on the edge devices while maintaining the inference time and high throughput is equally challenging. Model Quantization is the key to solving this problem.

The need for Quantization?

Now before going into quantization, let’s see why neural network in general takes so much memory.

Elements of ANN

As shown in the above figure a standard artificial neural network will consist of layers of interconnected neurons, with each having its weight, bias, and activation function. These weights and biases are referred to as the “parameters” of a neural network. This gets stored physically in memory by a neural network. 32-bit floating-point values are a standard representation for them allowing a high level of precision and accuracy for the neural network.

Getting this accuracy makes any neural network take up much memory. Imagine a neural network with millions of parameters and activations, getting stored as a 32-bit value, and the memory it will consume. For example, a 50-layer ResNet architecture will contain roughly 26 million weights and 16 million activations. So, using 32-bit floating-point values for both the weights and activations would make the entire architecture consume around 168 MB of storage. Quantization is the big terminology that includes different techniques to convert the input values from a large set to output values in a smaller set. The deep learning models that we use for inferencing are nothing but the matrix with complex and iterative mathematical operations which mostly include multiplications. Converting those 32-bit floating values to the 8 bits integer will lower the precision of the weights used.

Quantization Storage Format

Due to this storage format, the footprint of the model in the memory gets reduced and it drastically improves the performance of models. In deep learning, weights, and biases are stored as 32-bit floating-point numbers. When the model is trained, it can be reduced to 8-bit integers which eventually reduces the model size. One can either reduce it to 16-bit floating points (2x size reduction) or 8-bit integers (4x size reduction). This will come with a trade-off in the accuracy of the model’s predictions. However, it has been empirically proven in many situations that a quantized model does not suffer from a significant decay or no decay at all in some scenarios.

Quantized Neural Network model

How does the quantization process work?

There are 2 ways to do model quantization as explained below:

Post Training Quantization:

As the name suggests, Post Training Quantization is a process of converting a pre-trained model to a quantized model viz. converting the model parameters from 32-bit to 16-bit or 8-bit. It can further be of 2 types. One is Hybrid Quantization, where you just quantize weights and do not touch other parameters of the model. Another is Full Quantization, where you quantize both weights and parameters of the model.

Quantization Aware Training:

As the name suggests, here we quantize the model during the training time. Modifications are done to the network before initial training (using dummy quantize nodes) and it learns the 8-bit weights through training rather than going for conversion later.

Benefits and Drawbacks of Quantization

Quantized neural networks, in addition to improving performance, significantly improve power efficiency due to two factors: lower memory access costs and better computation efficiency. Lower-bit quantized data necessitates less data movement on both sides of the chip, reducing memory bandwidth and conserving a great deal of energy.

As mentioned earlier, it is proven empirically that quantized models don’t suffer from significant decay, still, there are times when quantization greatly reduces models’ accuracy. Hence, with a good application of post quantization or quantization-aware training, one can overcome this drop inaccuracy.

Model quantization is vital when it comes to developing and deploying AI models on edge devices that have low power, memory, and computing. It adds the intelligence to IoT eco-system smoothly.

At Softnautics, we provide AI and Machine Learning services and solutions with expertise on cloud platforms accelerators like Azure, AMD, edge platforms (TPU, RPi), NN compiler for the edge, and tools like Docker, GIT, AWS DeepLens, Jetpack SDK, TensorFlow, TensorFlow Lite, and many more targeted for domains like Multimedia, Industrial IoT, Automotive, Healthcare, Consumer, and Security-Surveillance. We can help businesses to build high-performance cloud-to-edge Machine Learning solutions like face/gesture recognition, human counting, key-phrase/voice command detection, object/lane detection, weapon detection, food classification, and more across various platforms.

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An Overview of Automotive Functional Safety Standards and Compliances

Quality Engineering / 21/04/2022

It has been observed that the frequency of traffic accidents has increased significantly over the last two decades, resulting in many fatalities. As per the WHO (World Health Organization) road safety report across the globe, about 1.2 million people lose their life on the roads each year, with another 20 to 50 million suffering quasi-injuries. One of the primary elements that have a direct impact on road user safety is the reliability of automobile devices and systems.

Autonomous vehicles are gaining immense popularity with the advancement in self-driving. Wireless connectivity and other substantial technologies are facilitating ADAS (Advanced Driver Assistant Systems), which consists of applications like adaptive cruise control, automated parking, navigation system, night vision & automatic emergency braking, etc, which play a critical role in the development of fully autonomous vehicles.

Safety Of The Intended Functionality SOTIF (ISO/PAS 21448) was created to solve the new safety challenges that software developers are encountering for autonomous (and semi-autonomous) vehicles. SOTIF (ISO 21448) refers to safety-critical functionality that necessitates sufficient situational awareness. By implementing these procedures, you can accomplish safety in situations where you might otherwise fail. SOTIF (ISO 21448) was designed to be ISO 26262: Part 14 at first. Since assuring safety in the absence of a system breakdown is so difficult, SOTIF (ISO 21448) has become its standard. Because AI and Machine Learning are the vital components of autonomous vehicles. The use of SOTIF (ISO 21448) will be critical in guaranteeing that AI can make appropriate judgments and avoid dangers.

Functional Safety – ISO 26262

FuSa (ISO 26262) automotive functional safety standard establishes a safety life cycle for automotive electronics, requiring designs to pass through an overall safety process to comply with the standard. As within the case of IEC (International Electrotechnical Commission), 61508 measures the reliability of safety functions and uses maximum probability while ISO 26262 is predicated on the violation of safety goals and provides requirements to realize a suitable level of risk. ISO 26262 validates a product’s compliance from conception to decommissioning to develop safety-compliant systems.

ISO 26262 employs the idea of Automotive Safety Integrity Levels (ASILs), a refinement of Safety Integrity Levels, to reach the objective of formulating and executing reliable automotive systems and solutions. ASILs are assigned to components and subsystems that have the potential to cause system failure and malfunction, resulting in hazards. The best allocation of safety levels to the system framework is a complicated issue that must ensure that the highest safety criteria are met while the development cost of the automobile system is kept to a minimum. Let us see what each part of this standard reflects.

Automotive Functional Safety Guidelines

Part 1 – Vocabulary: It relates to the definitions, terms, and abbreviations used in the standard to maintain unity and avoid misunderstanding.

Part 2 – Management of Functional Safety: It offers information on general safety management as well as project-specific information on management activities at various stages of the safety lifecycle.

Part 3 – Concept Phase: Analysis and assessment of risk are being evaluated in the early product development phase.

Part 4 – Product Development at the System Level: It covers system-level development issues comprising system architecture design, item integration & testing.

Part 5 – Product Development at the Hardware Level: It covers basic hardware level design and evaluation of hardware metrics.

Part 6 – Product Development at the Software Level: It comprises software safety, design, integration & testing of embedded software.

Part 7 – Production and Operation: This section explains how to create and maintain a production process for safety-related parts and products that will be installed in vehicles.

Part 8 – Support Processes: This section covers all stages of a product’s safety lifecycle, like proceeding to verification, undertaking tool qualification, documentation etc.

Part 9 – Automotive Safety Integrity Level (ASIL): It covers the requirement for ASIL analysis, defines ASIL decomposition state and analysis of dependent failures.

Part 10 – Guideline on ISO 26262: It covers an overview of ISO 26262 and other guidelines on how to apply the standard.

ISO 26262 classifies ASILs into four categories: A, B, C, and D. The lowest degree of automobile hazard is ASIL A, while the maximum degree is ASIL D. Since the dangers connected with their failure is the highest, systems like airbags, anti-lock brakes, and power steering require an ASIL-D rating, the highest level of rigor applied to safety assurance. Components like rear lights, on the other hand, are merely required to have an ASIL-A rating. ASIL-B would be used for headlights and brake lights, while ASIL-C would be used for cruise control.

Types-of-ASIL-classification

Types of ASIL classification

Automotive Safety Integrity Levels are determined by two factors such as analysis of hazard and assessment of risk. Engineers measure three distinct factors for each electronic component in a vehicle, and those are based on the following factors.

Intensity (the severity of the driver’s and passengers’ injuries)
Amount of exposure (how frequently the vehicle is subjected to the hazard)
Possibility of control (how much the driver can do to avoid an accident.)

MISRA C

The Motor Industry Software Reliability Association (MISRA) publishes standards for the development of safety and security-related electronic systems, embedded control systems, software-intensive applications, and independent software.

MISRA C contains components that protect automobile software from errors and failures. With over 140 rules for MISRA–C and more than 220 rules for MISRA–C++, the suggestions tackle code safety, portability, and reliability issues that affect embedded systems. For MISRA C compliance, developers must follow a set of mandatory rules. The goal of MISRA C is to provide the best performance in terms of software operation for software programs used in automobiles, as these programs can have a significant impact on the vehicle’s overall design safety. Developers utilize MISRA C as one of the tools for developing safe software for automobiles.

AUTOSAR

AUTOSAR (Automotive Open System Architecture) this standard’s goal is to provide a set of specifications that describe fundamental software modules, specify programmatic links, and implement common methods for further development using a standardized format.

AUTOSAR’s sole purpose is to provide a uniform standard across manufacturers, software suppliers, and tool developers while maintaining competition so that the result of the business is not harmed.

While reusability of software components lowers development costs and guarantees stability, it also increases the danger of spreading the same software flaw or vulnerability to other products that use the same code. To solve this significant issue, AUTOSAR advocates safety and security features in software architecture.

The design approach of AUTOSAR includes

Product and system definition including software, hardware, and complete system.
Allocating AUTOSAR to each ECU (Electronic Control Unit)
Configuration of OS, drivers, and application for each ECU (Electronic Control Unit)
Comprehensive testing to validate each component, at unit level and system level.

The necessity to assure functional safety at every level of product development and commissioning has grown even more crucial in today’s world when automotive designs have got increasingly complicated with many ECUs, sensors, and actuators. Therefore, today’s automakers are more concerned about adhering to the highest automobile safety requirements, such as the ISO 26262 standard and ASIL Levels.

At Softnautics, we help automotive businesses to manufacture devices/chipsets complying with automotive safety standards and design Machine Learning based intelligent solutions such as automatic parallel parking, traffic sign recognition, object/lane detection, in-vehicle infotainment systems, etc. involving FPGAs, CPUs, and Microcontrollers. Our team of experts has experience working with autonomous driving platforms, middleware, and compliances like adaptive AUTOSAR, FuSa (ISO 26262), and MISRA C. We support our clients in the entire journey of intelligent automotive solution design.

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