Due to high computing demands, SoCs are becoming more complex. Machine Learning, Multimedia, connectivity are critical factors for this. When developing SoC, the critical decision to be made is choosing the proper Instruction Set Architecture (ISA) and the processor hardware architecture. There are many ISA available having different pros and cons. Some of them are proprietary and licensable, while some of them are open. ARM and Intel are two populate players in processor architectures.

There are different variants of architectures provided by vendors. Significant benefits of using licensed architecture are already developed software and ready to use ecosystem. However, design flexibility is minimal with these architectures. Open-source ISA offers greater flexibility, and they are free. Having an open-source also makes room for continuous improvements. People can modify them as per their requirements and contribute back to make them better.

RISC-V (Reduced Instruction Set Computing) is an open standard instruction set architecture based on Reduced Instruction Set Computing (RISC) principles. The RISC-V architecture project was started in 2010 by Prof. Krste Asanović, Prof. David Patterson, graduate students Yunsup Lee and Andrew Waterman at the UC (University of California, Berkeley).

RISC-V is a royalty-free, license-free, and high-quality based ISA sets. The RISC-V standards are maintained by the RISC-V Foundation Company. The RISC-V Foundation is a non-profit organization formed in Aug 2015 to maintain its standards publicly. Currently, more the 230+ companies have been joined the RISC-V Foundation. The RISC-V is freely available under the BSD license. Well, the RISC-V is neither a company nor a CPU implementation.

How RISC-V is different than other processors?

Freely available
Unlike other ISA designs, the RISC-V ISA is provided under free licensing, which means that without paying any fees, we can still use, modify, and distribute the same.

Open Source
As RISC-V ISA is open source, people can use them and improve them. This makes the product more reliable.

Fully Customizable
Though there may be different proprietary processor cores, customization is not possible based on the requirement. The advantage of using the RISC-V ISA (Instruction Set Architecture) is that it enables companies to develop a completely customizable product, specifically to their requirements. They can start with the RISC-V core and add whatever is based on their need. This ultimately saves their time and money, resulting in low cost and low power products which can be used for a long time.

Support for user-level ISA extensions
RISC-V is very modular. There are many standard extensions available for specific purposes which can be added to the base as per requirement. Developers can also create their non-standard extensions. Some of the standard extensions used by RISC-V are:

• • M – Integer Multiplication and Division
  • I – Integer
  • A – Atomics Operation
  • F – Single-Precision Floating Point
  • D – Double-Precision Floating Point
  • Q – Quad-Precision Floating Point
  • G – General Purpose, i.e., IMAFD
  • C – 16-bit Compressed instructions

Designed 32/64/128 bits wide support
RISC-V has different bits width support providing more flexibility for the product development.

Riscv processor

Apart from the above benefits, RISC-V has many vital features like multicore support, fully virtualizable for hypervisor development.

The RISC-V supports different software privileged levels

• User Mode (U-Mode) – Generally runs user processes
• Supervisor Mode (S-Mode) – Kernel (Including kernel modules and device drivers), Hypervisor
• Machine Mode (M-Mode) – Bootloader and Firmware

The processor can run in only of the privilege modes at a time. The machine mode is the highest privileged mode and the only required mode. The privilege level defines the capabilities of the running software during its execution. This different level of models makes RISC-V a choice for certain & safety products.

One thing to note is RISC-V is open-source Instruction Set Architecture. Using this architecture, anybody can develop processor cores. Developed core can be free or proprietary depending on the choice of who develops it.

RISC-V can be used for a variety of applications because of its great flexibility, extensions, and possible customization. The RISC-V is suitable for all types of micro-processing systems to the super-computing system. It can fit into small memory devices consuming less memory & power. Similarly, its other variant can provide high computing capabilities. Its privileged modes can provide security features like trust zone & secure monitor calls.

Some of the applications suited for RISC-V are:

• Machine Learning edge inference
• Security solutions
• IoT

RISC-V for Security Solution

Softnautics is using Lattice Semiconductor RISC-V MC CPU soft IP to develop security solutions. The below diagram illustrates it in brief.

Security solution

In Safety-critical products, RISC-V works as the root of trust to ensure the authenticity and integrity of the firmware. It provides below functionalities:

• Protect platform firmware & critical data : It protects platform firmware and critical data from unauthorized access.
• Ensure authenticity & integrity of Firmware : On the boot, it checks for firmware signature and verifies that it is not tempered.

• Detect corrupted platform firmware & critical data : It checks platform firmware & critical data on boot and runtime when requested. If the platform or critical data gets corrupted for any reason, it can detect them and take corrective actions.

• Restore corrupted platform firmware and/or critical data : If platform firmware or critical data are corrupted, it performs restoration of platform firmware and/or critical data from the backup partition based on the requirement.

• Runtime monitoring for unintended access : During runtime, it monitors bus traffic accessing secure memories (e.g., SPI traffic) and blocks unintended access.

RISC-V for IoT solution

Gateway is developed with the RISC-V-based MCU to leverage the security features provided by RISC-V.

Riscv IoT solution

The gateway is developed to perform device management, user management, and services management. A cloud agent is developed to handle all the cloud activity from device to cloud via gateway. A device agent is developed to manage all the devices connected to the gateway. A service agent makes sure all the interface and status of the interface and connected device.

Read our success stories related to Machine Learning expertise to know more about our services for accelerated AI solutions.

Contact us at business@softnautics.com for any queries related to your solution or for consultancy.

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Industry Focus Towards Getting Maximum Performance with Optimum Power

With the latest evolution, performance per watt of power usage has become critical for any SoC. SoC designers are striving for energy conservation to manage the ultimate trade-off between power consumption and differentiating performance. Of greater importance are the application processors where a mere milliwatt of power consumption can make the difference between design win in the market-leading application or losing an opportunity to participate in the rapid growth market. SoC Power Management is gaining prominence in several traditional markets ranging from data center CPUs, automotive infotainment systems to IoT devices and wearables. In today’s world, SoCs are ideally expected to support a variety of use cases with optimum power levels.

Design Choices and Power Management Techniques in Complex SoCs

While CPUs, GPUs, and peripherals dominate SoC’s power management attention, other functional blocks are often overlooked. Today, interconnect technologies for accelerators & FPGA PLs also gain prominence in the SoC space with rising data center and cloud-oriented use-cases. More significant advantages have been realizable for those who have switched over to advanced Network-On-Chip (NoC) interconnect fabrics. Essential benefits of NoC are managing power consumption across  different functional blocks of the SoC and the interconnects between them, not just the CPU and GPU. Since the interconnect links all major available blocks, it provides an excellent opportunity to enhance best power management practices:

• Dynamic frequency and voltage scaling
• Data path optimization
• Different power islands
• Clock gating
• Adaptive voltage scaling
• Standby/leakage current management

Thus, NoC brings in a lot of advantages compared to older bus & crossbar interconnect technologies. To leverage the power management strengths of the NoC, SoCs will need a dedicated unit that can manage all the different resources depending on the application’s requirements, like Xilinx Versal ACAP’s PLM unit and ZynqMP Ultrascale+ MPSoC’s PMUFW unit.

Power management in Xilinx Versal ACAP

Source: Xilinx

Xilinx Versal ACAP has functional blocks in different power domains like LPD, FPD, PL, NoC, PMC, etc.

FP domain
Full Power Domain (FPD) is responsible for consuming high power. It mainly consists Cortex-A72 application processor for running a heavy application like Linux. It also has another high-power component like GPU, DP, PCIe, etc.

LP domain
Low Power Domain (LPD) mostly consists of small low-power peripherals like I2C, SPI, UART, etc. It also includes a cortex-R5 processor for running safety/secure/RTOS applications and on chip memories like OCM, TCM for faster memory access. This domain is also responsible for housing wakeup sources like UART, Ethernet, USB, etc.

PL domain
Programmable Logic (PL) domain includes DSP engine, Configurable logic block (CLB), Block RAM, Ultra RAM, and AI Engine blocks. This provides the improved application performance of the overall embedded system design.

NoC domain
The Network on Chip (NoC) provides the interconnects for the entire SoC units. It provides the connection between master and slave on an AXI4-based network and maps the global address space based on NoC interconnect.

PMC domain
Platform Management Controller (PMC) runs platform management firmware, which provides the platform management for the entire ACAP. The firmware running on PMC can manage the peripherals and power domains depending upon the user applications.

The power numbers of ACAP ranges from hundreds of watts to microwatts depending on the configuration. The individual power domains can be entirely powered down so that its power requirement, including static power, becomes virtually zero. Xilinx provides extensive software support for Power Management in the U-boot, ATF, Xen, Linux, and the BareMetal application.

Softnautics, with its rich experience in Platform Management on Xilinx Ultrascale+ MPSoC, was one of the early entrants into Versal ACAP platform management, supporting Xilinx extensively in developments across software layers in ATF, Xen, Linux, and BareMetal level. Going further, Softnautics has scaled up to keep some of the key end-customers of Xilinx.

Some of the key features implemented in power management on Versal ACAP by Softnautics are:

Linux suspend/resume with different wakeup sources

• APU (Cortex-A72 runs Linux on the Versal ACAP can configure different peripherals such as UART, Ethernet (Wakeup on LAN), USB, etc. The Platform Management Controller (PMC) has been configured to handle multiple wake-up sources appropriately activated when the user suspends the system. This allows a complete power down of the Full Power Domain (FPD) domain.
• When the wakeup source device generates a wakeup event, PMC gets the interrupt and powers up the FPD and APU running Linux.>

Xilinx’s Versal ACAP is a differentiating platform that will transform the horizon of power-hungry applications while smartly conserving energy and ensuring the best performance. Softnautics aims to continue playing key roles with its highly skilled talent pool to enable end-to-end solutions, leveraging Versal ACAP advancements in platform and power management.

Read our success stories related to Machine Learning expertise to know more about our services for accelerated AI solutions.

Contact us at business@softnautics.com for any queries related to your solution or for consultancy.

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Xilinx research shows its Ultrascale+TM XCVU13P FPGA (38.3 INT8 TOP/s) platform provides the same computing power as Tesla P40 (40 INT8 TOP/s) but flexibility and on-chip memory on Xilinx device results in significantly higher computing capability for different workloads and apps. Another Xilinx research in a general-purpose compute efficiency shows its Virtex Ultrascale+ performing 4x better than Nvidia Tesla V100. The scales tilt further in favor of FPGAs when we consider functional safety demanded by safety-critical aviation, autonomous automotive, and defense applications, such as ADAS.

Embedded Vision requires the machines which have the ability to see, sense, and quickly respond to challenges the hardware designers create next-gen architecture that is highly differentiated and extremely responsive to adapt to ever-evolving algorithms and image sensors.

If the ones mentioned above are computing power-intensive use-cases that need to utilize custom neural networks (CNNs/DNNs), the other side of the spectrum requires extremely low-power operations with a flexible solution building approach.

In pursuit of maximizing the efficiency of machines to achieve higher throughput of operations, the Industrial Internet of Things (IIoT) is driving Industry 4.0. Such applications require a combination of software programmability coupled with real-time processing of sensor data to leverage any-to-any connectivity in a secure and safe manner. The flexible nature of FPGA programmability and low-power consumption make FPGAs a perfect choice for Industry 4.0 solutions.

It is just the beginning of how FPGA platforms are powering the ML solutions that are likely to see mass-adoption and become household essentials as we create diverse use-cases to help people, businesses, and governments to make the world a safer and smarter place
Know how Softnautics can help you design FPGA-Powered ML solution for your use-case.